Google is developing custom silicon to power our direct-to-consumer hardware. This role contributes to high-performance, low-power block designs for CPUs, GPUs, or SoCs, collaborating across RTL, Architecture, and DFT teams.
You will lead block-level implementation, signoff, and QoR analysis with emphasis on timing, power, and area in a fast-paced hardware environment based in Mountain View, CA or preferred location. Competitive compensation includes equity and bonus.
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