We are seeking a Design Verification Engineer to develop and maintain UVM-based verification environments for CPU subsystems.
Responsibilities
- Verify CPU cores, pipelines, and instruction execution
- Implement constrained-random testing and advanced testbench architectures
- Integrate Instruction Set Simulators (ISS) with DV environments
- Debug complex functional issues across hardware and testbench
Requirements
- Strong SystemVerilog and UVM skills
- Experience in CPU/processor verification and testbench architecture
Preferred
- Familiarity with ISS (e.g., Spike)
- Experience with random instruction generators (e.g., Sting)
- Knowledge of processor software toolchains
Pay Range: $70 - $85/hr on w2 (All inclusive)
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