CPU Design Timing Engineer: Drive High-Performance Timing Closure

Apple, Inc. is seeking a CPU Design Timing Engineer in Austin to lead timing closure across CPU projects. You will collaborate with CAD, RTL and implementation teams to craft timing flows and automate analyses using TCL, Perl or Python. Experience with high-performance CPU timing, cross-domain design, and physical design tools is preferred.

The role emphasizes hands-on timing work, tool flows, and the ability to optimize for 1 GHz+ designs in a fast-paced hardware environment.