CPU Clock Design Engineer – Low-Power, Low-Skew

Qualcomm Technologies, Inc. is seeking a Physical Design Clock Engineer in Austin, TX (open to Santa Clara) to drive clock generation and distribution for next-gen CPU architectures.

You will collaborate with RTL, CAD, and physical design teams to optimize clock skew, power, and performance, performing jitter analysis and validating clocking across designs. A strong background in electrical engineering and hardware verification is required.