Contract Physical Design Engineer

• Strong end-to-end RTL-to-GDS flow experience:
• APR (Automatic Place & Route) experience is a key requirement.
• 3nm FinFET process experience is highly preferred/important.
• Strong GDS/GDSII and STA (Static Timing Analysis) experience required.
• Strong experience with Clock Tree / CTS, Timing Closure, and Signoff .
• Synopsys Compiler tools are highly desirable.
• Day-to-day work will primarily involve RTL blocks, Clock Tree, Timing, and Signoff activities.
• Candidates should have strong hands-on ASIC Physical Design / Implementation experience.

Preferred Candidate Background:

• Candidates from Broadcom, Google, Intel , etc. are highly preferred.
• Preference for candidates with experience in advanced-node semiconductor projects , especially 3nm FinFET .

Duration:

• Potential extension: 1 additional year
• Expected total duration: up to 1 year 3 months , depending on project requirements.