ET_TN01
Title: Contract Hardware Engineer Mid. (Analog Mix Signal)
Location: San Jose CA (Day-1 Onsite)
Duration: 12 Months
Experience: 8+ Years
Note: Seeking an Analog Mixed signal Design have experience on PLLs, ADCs/DAC and FinFET (e.g., 16nm, 7nm...) nodes.
What candidate will Be Doing:
Education:
Title: Contract Hardware Engineer Mid. (Analog Mix Signal)
Location: San Jose CA (Day-1 Onsite)
Duration: 12 Months
Experience: 8+ Years
Note: Seeking an Analog Mixed signal Design have experience on PLLs, ADCs/DAC and FinFET (e.g., 16nm, 7nm...) nodes.
What candidate will Be Doing:
- Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
- What we are looking for:
- Design Experience: 8-12+ years of hands-on experience in analog IC design.
- Circuit Architecture & Design : Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
- EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, HSPICE, or CustomSim.
- Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools
- Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm...) nodes.
- Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
- Methodology: Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).
Education:
- Bachelor's and/or Masters
Contract Hardware Engineer Mid. in san jose at Unknown Company
This position is listed as contract and onsite.