Annapurna Labs (U.S.) Inc. in Austin, TX is seeking an ASIC Design Engineer to drive RTL/SOC integration for high-performance machine learning accelerators.
You will design, implement and optimize RTL, meet timing, power and area targets, and collaborate with cross-functional teams across verification, synthesis and back-end processes. The role emphasizes SystemVerilog RTL, micro-architecture exploration, and strong debugging skills, with a focus on scalable server-grade hardware within AWS
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