TYLsemi is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization of the chiplet using industry-standard ESL tools or in-house solutions.
You will own the trade-off analyses that define tape-out decisions, build transaction-level models with ESL suites, sweep hardware parameters, and collaborate with IP vendors to integrate PCIe, UCIe and NoC into a full-chiplet model.
#J-18808-LjbffrChiplet Performance & Power Architect — Remote-Friendly in san jose at Unknown Company
This position is listed as full time and onsite.