A leading staffing and recruiting firm is seeking a Design Verification Engineer in San Jose, California. This role requires skills in UVM, UPF, VIP, System Verilog, VHDL, and SOC verification, with Python or TCL experience beneficial. The position is for contract employment aimed at Associate level candidates working in design-focused management. Ideal for those looking to enhance their expertise in a fast-paced technology environment.
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Associate Design Verification Engineer - UVM SystemVerilog in san jose at Unknown Company
This position is listed as contract and onsite.