ASIC Timing Design & Sign-off Engineer

Apple Inc. in Waltham, MA is seeking an ASIC STA Engineer to manage all aspects of SoC timing from synthesis to sign-off. You will own timing sign-off, develop STA flows, and collaborate with RTL, CAD and Physical Design teams to drive timing closure.

The ideal candidate has a BS in Electrical Engineering with 2+ years in ASIC timing, strong Primetime skills, and proficiency in Tcl/Perl scripting. Strong cross-team communication is essential.