Amazon Energy? Annapurna Labs (U.S.) Inc. is seeking a skilled SSTA engineer to design and optimize timing flows for ASICs in Cupertino. You will develop timing constraints, run STA, and collaborate with RTL/Arch teams to deliver high-performance, cost-efficient silicon.
The role emphasizes automation, mentoring, and close teamwork within a fast-paced startup-like environment, with a strong focus on delivering reliable, scalable timing solutions.
#J-18808-LjbffrASIC Timing & Physical Design Engineer in cupertino at Unknown Company
This position is listed as full time and onsite.