ASIC STA Engineer: Timing Closure & IP Integration

Apple seeks an ASIC STA Engineer to lead timing closure across full chip and blocks, coordinating with SoC Design, Verification, DFT, Architecture and Physical Design teams. You will work with CAD/Flow teams to refine front-end timing methodologies and develop robust timing analysis flows.

The role requires a strong foundation in digital design and familiarization with Primetime, Synthesis, and timing concepts. You’ll be a self-motivated communicator driving cross-group collaboration.