Apple Inc. in Cupertino seeks an ASIC STA Engineer to lead timing closure across complex SoCs. You will own timing closure for full chips and blocks, guiding timing verification and constraint generation across projects.
Work with multi-functional teams to resolve timing issues in deep sub-micron technologies. Strong digital design fundamentals and scripting in TCL/Perl are valuable, with Primetime familiarity a plus.
#J-18808-LjbffrASIC STA Engineer: Timing Closure & IP Delivery in cupertino at Unknown Company
This position is listed as full time and onsite.