This is a Senior/Staff-level ASIC/RTL Design Engineer role requiring 10+ years of industry experience in end-to-end SoC design. The strongest candidates should have hands-on expertise in RTL coding, micro-architecture, ASIC design flow, verification/debug, synthesis, timing closure, and silicon bring-up, with experience leading complex digital designs.
Core requirements:
- 10+ years of ASIC/RTL/SoC Design experience.
- SoC architecture and micro-architecture development.
- Experience with complete ASIC design flow.
- Synthesis and timing closure.
- Experience with ARM cores.
- Knowledge of high-speed interfaces such as: PCIe, DDR/DDR4/DDR5, Ethernet, DMA, SATA.
- Experience working with physical design, software, emulation, and silicon bring-up teams.