Xcelerium, located in Irvine, CA, is seeking an ASIC RTL Design Engineer to develop high-performance, low-power digital designs and RISC-V cores. You will collaborate with various teams to optimize designs, ensuring quality and efficiency.
This role requires a Bachelor's degree in engineering and over 5 years of experience. A strong understanding of Verilog/SystemVerilog and a passion for technology will be essential for success in this innovative environment.
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