We are looking for highly experienced ASIC Physical Design / Static Time Analysis (PD/STA) Engineerto work onsite in our St. Paul, MN office to support ASICs, IPs and Chiplet designs. This role is targeted at senior level candidates who can operate with a high degree of RTL2GDS PD implementation and sign-off for tape out.
Key Responsibilities
- Lead and collaborate with Analog, Verification, Logic and Physical design team members on all design implementation aspects from Synthesis to Tape-Out of various IPs, test chips and SoC/ASIC designs.
- Lead with hands-on experience with synthesis, block and chip level implementation with industry standard PnR, STA and EMIR flows and tools
- Lead end-to-end timing closure at block/chip levels including MCMM flows and ECO flows
- Collaborate with cross functional teams to problem solve solutions across new and changing tools, flows and methodologies
- Mentor junior and senior PD engineers through technical reviews, methodology guidance, and hands-on support.
- Improve productivity through automation, infrastructure, and methodology enhancements.
- Support project planning by identifying risks, tracking progress, and communicating status to technical and program leadership.
Qualifications
- BS in Electrical, Electronics, Computer Engineering, or 15 years of experience in related field or MS in Electrical, Electronics, Computer Engineering, or 12 years of experience in related field or Ph.D. with 8 years of experience in related field
- Experience in advanced technology nodes and understanding of deep sub-micron design problems/solutions and ability to drive design closure in a fast-paced environment
- Strong experience in SOC/ASIC design flows, tools and methodologies.
- Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques
- Excellent understanding of logic design fundamentals and gate/transistor level implementation
- Strong programming skills in Tcl/Perl/Shell/Python
- Effective communicator with the ability to influence cross-functional teams.
What We Offer
- Work-Life Balance: Flexible 9/80 work schedule with every other Friday off
- Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO
- Incentives: Eligibility for short-term and long-term incentive programs
ASIC Physical Design Engineer in saint paul at Unknown Company
This position is listed as full time and onsite.