NVIDIA in Santa Clara, CA is seeking a skilled CPU design engineer to contribute to the physical design of the on-chip interconnect network and last-level caches, collaborating with the RTL/logic teams on micro-architecture feasibility and optimization. You will drive synthesis, timing closure, and power-performance trade-offs while evaluating interconnects and system caches for next-generation products.
This role emphasizes high-frequency design, HDL/RTL flow, and cross-functional teamwork in a
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