ASIC Logic Design Engineer – RTL, Timing, Interconnect

NVIDIA in Santa Clara is seeking a Logic Design Engineer to join the CPU Logic Design Team. You will define micro-architectural aspects of on‑chip interconnect, coherency and last‑level caches, and contribute to RTL coding, synthesis and timing closure.

You will deliver a focused unit, write high‑quality RTL, collaborate with verification and implementation teams to meet timing, area and power goals, and support lab debug and bring‑up.