HyperLume in San Jose, CA is seeking a Front-end ASIC Design Engineer to lead RTL implementation and verification of complex logic blocks. Collaboration with PD, DFT, STA, and integration teams will ensure successful tape-outs and support chip bring-up and validation.
The role involves close coordination with cross-functional teams to deliver robust ASIC designs ready for production in a fast-paced earthtech ecosystem.
#J-18808-LjbffrASIC Front-End Design Engineer – RTL & Verification in san jose at Unknown Company
This position is listed as full time and onsite.