Silicon One Team At CiscoJoin the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As a member of the team, you will contribute to defining innovative ASIC STA methodologies and creating robust flows essential for developing our complex chips.Your ImpactDefine, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms.
Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.What You'll DoOversees the definition, architecture and design of high performance ASICsOversees all applications and code including methodology of reusable codeOversees code creation and determines methodology behind codingConsults for architecture and design decisions for complex areasDrives design solutions across the businessCreates guidelines and standardsCreates innovative verification strategiesOversees system level verification using test benchesEnsures culture of code reviews and postmortemsArchitects and designs analog/mixed-signal circuitsReviews complex IC designs and makes recommendations for improvementsDirects the mixed-signal team to define requirements, influences packaging and hardware team to ensure specifications are metOversees all physical design functions bringing technical expertise to highly complex scenariosInterfaces with vendors and design leads on complex issuesDrives different technology design rules to develop innovative packagesMinimum QualificationsBachelor's with 10 years of related experience, or Master's with 5 years of related experience, or PhD with 2 years of related experience.Prior experience with Integration for STA including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.Prior experience in developing timing constraints and signing off timing on blocks/sub system in advanced process nodesPrior experience with timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery.Prior experience with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.Preferred SkillsSynthesis Tools: Synopsys.
DC/DCG/FCFormal Verification : Synopsys, Formality and Cadence LECParasitic Extraction : Synopsys, Star-RCXT, Cadence QuantusStatic Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence TempusScripting: TCL, Perl is required; Python is a plus