Responsibilities
- Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms
- Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products
- Design, document, and develop ASIC subsystems for release in high volume and quality
- Help define the process, methods, and tools for design and implementation of complex developments
- Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
- Design and implement robust and reusable RTL with CDC/RDC considerations
- Spec comprehensive CDC/RDC check flows and work with CAD team to implement
- Review and approve CDC/RDC constraints and waivers
- Perform static glitch analysis
- Improve design with prevention of static glitch hazard
Requirements
- Bachelor’s with 8+ years or related experience, or master’s with 6 + years of related experience, or PhD + 3 years of related experience
- Prior experience with RTL development skills and experiences
- Prior experience with CDC/RDC concepts and relevant design implementation
- Prior Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
- Prior experience with static glitch hazards and relevant analysis on synthesis optimized gate netlists
- Experience on SDC constraints development (Preferred)
- Experience on VCS simulation SVA (SystemVerilog Assertions) (Preferred)
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