NVIDIA seeks an ASIC Design Efficiency Engineer to innovate HW/RTL for next-generation GPUs and processors across mobile, embedded, and data center platforms. You will contribute to design targets, performance, and power-efficiency enhancements while collaborating with architects and VLSI teams.
The role requires a strong background in HDL, logic design, and system architecture, with a focus on efficient, scalable design methodologies and cross-disciplinary teamwork. #J-18808-Ljbffr
ASIC Efficiency Engineer: Boost PPA, GPUs & Equity in santa clara at Unknown Company
This position is listed as full time and onsite.