ASIC Digital Design Tech Lead

Digital Design Technical Leader For Silicon One OpticsAs a Digital Design Technical Leader for Silicon One Optics, you won't just be building chips—you will architect the backbone of next-generation optical interconnects. From initial concept to tapeout and post-silicon production, you will own the full ASIC lifecycle and lead cross-functional engineering teams across digital, analog, firmware, and physical design.In this high-stakes role, you will define digital architectures, spearhead the integration of cutting-edge high-speed IPs (ODSP, D2D IP, SerDes XSR/PAM4), and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. This is your opportunity to drive technical strategy, pioneer breakthrough interconnect innovations, and deliver silicon that powers the future of high-performance computing.Minimum QualificationsBachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experiencePrior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validationPrior experience in managing the complete ASIC/SoC design flowPrior experience with key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed SerDes, Ethernet, and D2D PHY IP.Preferred QualificationsEnd-to-End Silicon Lifecycle & Architecture: Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.Specification & Microarchitecture Design: Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware vs.

firmware trade-offs.Verification, Simulation & IP Integration: Prior experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating SerDes and DSP IP.Implementation, Backend & Automation: Hands-on experience with backend implementation activities—including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.Cross-Functional Leadership: Prior experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.