ASIC DFT Engineering Technical Leader

ASIC Implementation Technical LeadThe Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.As a member of this team, you will also be involved in crafting groundbreaking next-generation networking chips.You will help lead to drive the DFT and quality process through the entire Implementation flow and post-silicon validation phases with additional exposure to physical design signoff activities.Ability to work with ATE engineers on pattern translation and validation.Minimum QualificationsBachelor's degree in Electrical or Computer engineering and 8+ years of experience, or Master's degree in Electrical Engineering or Computer Engineering and 6+ years of experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of experiencePrior experience with ATPG and EDA tools like TestMax or Tetramax or Tessent or similar tool setsPrior experience working with Gate level simulation, including timing-based simulations with SDF, debugging with VCS and other simulatorsPrior post-silicon validation and debug experiencePrior experience with scan insertionPreferred QualificationsVerilog design experience - developing custom DFT logic & IP integration; familiarity with functional verificationPrior experience with EDA tools like TessentPrior experience with Jtag protocols (p1500, p1687)Prior experience with SSNScripting skills: Tcl, Python/PerlPrior experience with test static timing analysis constraints development and timing closure