ASIC Design STA Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Role

AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate’s responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL‑based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front‑end (RTL) processes and back‑end (Synthesis and P&R) processes is preferred.

Key Responsibilities

• Develop complex multi‑mode/multi‑corner timing constraints that are compatible for RTL and signoff
• Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, automating the process for increased efficiency
• Implement pre‑route timing checks and QoR clean‑up to eliminate timing constraint issues and ensure a quality handoff for STA checks
• Collaborate with CAD on the development of pre‑production synthesis (Design Compiler) and STA (PrimeTime) workflows

Preferred Experience

• Worked with EDA tools that enable RTL quality checks
• Hands‑on experience building timing constraints for IPs, blocks and full‑chip implementation in both flat and hierarchical flows
• Experience analyzing timing reports and identifying design and constraint related issues
• Ability to multitask, grasp new flows/tools/ideas
• Experience improving methodologies
• Preferred EDA tool experience: Synopsys Design Compiler/PrimeTime, Spyglass, Fishtail, etc.
• Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
• Writing custom TCL QC and QoR checks using DC/PT object attribute queries and filters
• Strong analytical and problem‑solving skills

Academic Credentials

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering or a related field

Location

San Jose, CA

This role is not eligible for visa sponsorship.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.