ASIC Design Engineer: RTL & Microarchitecture, Equity

NVIDIA Corporation in Santa Clara, CA, seeks an ASIC Design Engineer to develop high-performance RTL for SoC and GPU products. You will draft microarchitecture, implement RTL in Verilog, and collaborate with architects and verification teams to deliver verified builds.

The role requires 2+ years of RTL experience, strong micro-architecture skills, and proficiency in Verilog, Python, and Perl. Equity and benefits accompany the base compensation, with a salary range disclosed for Levels 2 and 3.