ASIC Design Engineer: RTL & Microarchitecture, Equity

NVIDIA is seeking an ASIC Design Engineer in Santa Clara to build powerful SoC and GPU products. You will draft microarchitectures, implement RTL in Verilog, and drive verification across multiple IPs including GPU components.

The role requires 2+ years of RTL experience, strong Verilog skills, and proficiency in Perl/Python. You will collaborate with architects and verification teams to ensure high-performance, area- and power-efficient designs.