ASIC Clocking Engineer — PPA, RTL & Silicon, Equity

NVIDIA Corporation is seeking an ASIC Clocking Engineer to architect the clock domain for GPU/CPU, balancing functional, physical and testing requirements. You will collaborate across design, floorplanning, and lab teams to deliver robust clocking solutions and improve PPA across DFx, timing, and power.

You will work with Verilog RTL, verification and scripting to implement scalable clocking topologies, contributing to silicon bringup and end-to-end ASIC cycles.