AI SoC Cache Architect

Intel is seeking a senior SoC Cache Design Engineer to advance the cache subsystem for AI SoCs. You will define microarchitecture, code RTL in Verilog/SystemVerilog, and drive verification, timing, and bring-up across multiple US locations.

You will partner with verification and physical design teams to ensure power, performance, and area targets are met. The role emphasizes leadership, collaboration, and hands-on RTL development for cutting-edge AI hardware solutions.