Acceler8 Talent in Mountain View, CA seeks a Package Layout Engineer to own the physical design of advanced semiconductor packages for AI accelerators, leading end-to-end substrate and interposer layouts from stackup definition to tapeout, in collaboration with silicon, SI/PI, and PCB teams.
Responsibilities include bump mapping, 2.5D/3D integration, high-density RDL routing, power/ground networks, and OSAT coordination to meet manufacturing requirements.
#J-18808-LjbffrAI Hardware Package Layout Engineer - 2.5D/3D, Onsite in ca at Unknown Company
This position is listed as full time and onsite.