Velaura is seeking a Design Verification Engineer to help verify its next‑generation Physical AI SoC focused on AI acceleration units. You will verify hardware correctness, performance, and numerical behavior from RTL blocks to full systems, collaborating with architects, RTL engineers, software teams and system teams.
The role emphasizes creating test and coverage plans, developing reference models for GEMM/GEMV, and validating data flow, precision, and performance per watt under representative
#J-18808-LjbffrAI Accelerator Verification Lead in santa clara at Unknown Company
This position is listed as full time and onsite.