TSMC Technology, Inc. is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to drive physical design checks and ECO-based timing closures.
The role involves DRC/LVS/EM analysis, floorplanning, and clock-tree customization in a hybrid work model with four days in office. The candidate should have a Master’s degree in electrical engineering or CS, strength in RTL, Python, and EDA tools, and a background in design verification or related internships.
#J-18808-LjbffrAdvanced Physical Design & Verification Engineer – Hybrid in san jose at Unknown Company
This position is listed as internship and hybrid.