Advanced-Node ASIC Physical Design Engineer

Cisco is seeking a Physical Design Engineer to drive RTL-to-GDSII implementation for advanced semiconductor nodes, optimizing floor planning, timing, and backend design flows. You will collaborate across RTL, DFT, and EDA teams to deliver high-performance networking ASICs.

Responsibilities include hierarchical floor planning, place & route, clock and power distribution, timing convergence, and automation via scripting; preferred tools include Cadence Innovus, Synopsys tools, and PrimeTime.