Job TitleQualcomm Memory Design/Technology Team OpeningCompanyQualcomm Technologies, Inc.Job AreaEngineering Group, Engineering Group > ASICS EngineeringGeneral SummaryQualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform edge AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.Job OverviewThe Qualcomm Memory Design/Technology Team has an opening in the areas of System PDN and power modeling. The candidate will assess and optimize the high-performance chip and across-chiplet PDN architecture to ensure robust high-performance and low-noise compute.
The candidate will assess the best use of on-die, backside, and chiplet interconnect resources to determine the best power grid with minimum overhead to the system fabrics such as high-bandwidth bus, compute cores, and low-noise high-speed IOs for applications spanning high-performance cloud, compute, mobile and IoT. The candidate will work on robust PDN solutions along with power modeling addressing reliability, noise, and performance requirements from PMIC, to the package, and on-die power rail. The candidate is expected to understand the concepts of power distribution network, decoupling capacitance, power integrity, and power modeling. This position offers the opportunity to work across multiple organizations such as process and packaging team, system power team, and global SoC team. Providing timely feedback and updating PDN architecture and design trade-offs to the team is essential.ResponsibilitiesDevelop and optimize PDN memory and computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W for mobile, compute, and XR applicationsDevelop and validate models for power and power density modeling of multiple modules under different workloadsIdentify critical power scenarios and provide solutions within the constraints of packaging, floorplan, and PMIC moduleDevelop PDN models in both time and frequency domainSimulate and emulate system power behavior on different power scenarios such as power-up, power-down, maximum performance, test/debug, and stand-byIdentify locations of power switches and utilize optimal control mechanismsFloorplan 2.5/3D PDN under integration manufacturing constraints, testability, repairability, and high performanceMinimum Qualifications• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.Preferred QualificationsMaster's or Ph.D. in Electrical Engineering or a related fieldExperience in PDN, optimal decoupling capacitance placement, and power modelingExperience in modeling resonances on chips and 2.5D systems through resistance, inductance, and capacitance extractionGood knowledge of signal and power integrity, and chipletsGood knowledge of in the modeling of interconnects, uBumps, TSVs, and packageGood knowledge of cross-power domain structures, clamping, and ESD protection schemesGood knowledge of PMIC architecture, design, and noise modelingProficiency in use of EDA tools such as Voltus, Redhawk, SPICE, VirtuosoExperience in circuit and system design to model the power architectureExperience in memory architecture power assessmentExperience in model order reduction of large RLC networksFamiliar with memory architectureAbility to develop IBIS/Verilog-A/Modeling models of power modeling is strong plusFamiliar in thermal modeling and hotspot mitigationExperience in programming language (C/C++/Phyton) or scripting language (Perl/Python)Familiar with high-frequency signal assessmentPay Range and Other Compensation & Benefits$192,000.00 - $288,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).
In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.