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SoC Power Architect, Devices and Services, Silicon

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Bengaluru, Karnataka • Posted Recently
Onsite Full Time HARDWARE_ENGINEERING

Minimum qualifications:

  • Bachelor's degree in Electronics or Computer Engineering or equivalent practical experience.
  • 8 years of experience in ASIC power management or low power design methodology.
  • Experience with ASIC low power flows and power management concepts.

Preferred qualifications:

  • Master's degree in Electronics or Computer Engineering or equivalent practical experience.
  • Experience with SoC/System-level power modeling and estimation, defining power targets, power roll-ups, power/voltage domains design and low power architectures/optimization techniques (e.g., clock gating, power gating, multi Vth, DVFS).
  • Knowledge of the impact of software and architectural design decisions on system power and thermal behavior.
  • Familiarity with PMIC, SMPS, LDO and power delivery networks.
  • Excellent understanding of mobile SoC architectures and data flows, and experience with path-to-DDR IPs (e.g., Fabrics, System Cache, Memory Controller, DDRPHY, DRAM).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Define and drive low power solutions for Google SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints with a focus on path-to-DDR IPs (Fabrics, System Cache, Memory Controller, DDRPHY, DRAM, etc.).
  • Define power KPIs and SoC/IP-level power targets, guide architecture, design and implementation to achieve power targets, create power models, perform power roll ups and track power throughout the design cycle
  • Propose and drive power optimizations throughout the design process from concept to mass productization.
  • Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
  • Perform post-silicon characterization and productization of power features.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Additional Information

Published
2026-07-03T06:39:11.981Z
Url
https://careers.google.com/jobs/results/72676994948440774-soc-power-architect/
Jobtype
FULL_TIME
Employer
Google
Languagecode
en-US
Remote
onsite
Isremote
No
Ishybrid
No
City
Bengaluru
State
Karnataka
Country
India
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